MTech Cad Tools For Vlsi Design syllabus for 2 Sem 2020 scheme 20EMS23

VLSI Physical Design Automation:

VLSI Design Cycle, New Trends in VLSI Design Cycle, Physical Design Cycle, New Trends in Physical Design Cycle, Design Styles, System Packaging Styles.

Design and Fabrication of VLSI Devices:

Fabrication Materials, Transistor Fundamentals, Fabrication of VLSI Circuits, Design Rules, Layout of Basic Devices.

Data Structures and Basic Algorithms:

Basic Terminology, Complexity Issues and NP-hardness, Basic Algorithms, Basic Data Structures, Graph Algorithms for Physical design.∎

Partitioning:

Problem Formulation, Classification of Partitioning Algorithms, Group Migration Algorithms, Simulated Annealing and Evolution, Other Partitioning Algorithms, Performance Driven Partitioning.

Floor planning and Pin Assignment:

Floor planning, Chip planning, Pin Assignment, Integrated Approach.

Placement:

Problem Formulation, Classification of Placement Algorithms, Simulation Based Placement Algorithms, Partitioning Based Placement Algorithms, Other Placement Algorithms, Performance Driven Placement.

Global Routing:

Problem Formulation, Classification of Global Routing Algorithms, Maze Routing Algorithms, Line-Probe Algorithms, Shortest Path Based Algorithms, Steiner Tree based Algorithms, Integer Programming Based Approach, Performance Driven Routing.

Detailed Routing:

Problem Formulation, Classification of Routing Algorithms, Single-Layer Routing Algorithms, Two-Layer Channel Routing Algorithms, Three-Layer Channel Routing Algorithms, Multi-Layer Channel Routing Algorithms, Switchbox Routing Algorithms.

Course outcomes:

At the end of the course the student will be able to:

• Discuss design automation field including the VLSI design cycle, physical design cycle, design styles and packaging styles.
• Discuss the fabrication process for VLSI devices, process innovations, design rules and costs involved in fabrication process. .
• Explain data structures for layout and algorithms involved in the physical design.
• Explain graphs used to model problems in VLSI design and algorithms for the graphs.
• Explain partitioning, partitioning algorithms, their classification and the factors that must be considered in partitioning the VLSI circuits.
• Discuss algorithms for floorplanning and pin assignment and techniques for placement.
• Discuss global routing, routing algorithms and routing of multi-terminal nets
• Discuss detailed routing, routing algorithms and their classification.

Question paper pattern:

The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to 60.

• The question paper will have ten full questions carrying equal marks.
• Each full question is for 20 marks.
• There will be two full questions (with a maximum of four sub questions) from each module.
• Each full question will have sub question covering all the topics under a module.
• The students will have to answer five full questions, selecting one full question from each module.

Text Book

1. Algorithms for VLSI Physical Design Automation, Naveed A. Sherwani, Kluwer Academic Publishers, 3 rd Edition, 2002.