MTech System Verilog syllabus for 2 Sem 2020 scheme 20EVE23

Verification Guidelines:

The verification process, basic test bench functionality, directed testing, methodology basics, constrained random stimulus, randomization, functional coverage, test bench components, layered testbench.

Data Types:

Built in Data types, fixed and dynamic arrays, Queues, associative arrays, linked lists, array methods, choosing a storage type, creating new types with type def, creating user defined structures, typeconversion, Enumerated types, constants and strings, Expression width.

Procedural Statements and Routines:

Procedural statements, Tasks, Functions and void functions, Task and function overview, Routine arguments, returning from a routine, Local data storage, time values.

Converting the test bench and design:

Separating the test bench and design, The interface construct, Stimulus timing, Interface driving and sampling, System Verilog assertions.

Randomization:

Introduction, Randomization in System Verilog, Constraint details, Solution probabilities, Valid constraints, Inline constraints, Random number functions, Common randomization problems, Iterative and array constraints, Random control, Random Number Generators.

Threads and Interprocess Communication:

Working with threads, Disabling threads, Interprocess communication, Events, semaphores, Mailboxes, Building a test bench with threads and Interprocess Communication.

Functional Coverage:

Coverage types, Coverage strategies, Simple coverage example, Anatomy of Cover group and Triggering a Cover group, Data sampling, Cross coverage, Generic Cover groups, Coverage options, Analyzing coverage data, measuring coverage statistics during simulation.

Course outcomes:

At the end of the course the student will be able to:

1. Write test benches for moderately complex digital circuits

2. Use System Verilog language 3. Appreciate functional coverage

4. Apply constrained random tests benches using System Verilog

5. Analyze a verification case and apply System Verilog to verify the design

Question paper pattern:

The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to 60.

• The question paper will have ten full questions carrying equal marks.
• Each full question is for 20 marks.  There will be two full questions (with a maximum of four sub questions) from each module.
• Each full question will have sub question covering all the topics under a module.
• The students will have to answer five full questions, selecting one full question from each module.

Students have to conduct the following experiments as a part of CIE marks along with other Activities:

1. Write a program to demonstrate two-state and four-state data types.

2. Write a program to demonstrate push_front, pop_front, push_back and pop_back with respect to Queues.

3. Declare four variables red, black, white and green through Enumerated type declaration, use the keywords ‘first’ and ‘next’ to step through the variables and display the output.

4. Demonstrate Full adder with ‘Interface’ construct.

5. Write a program to demonstrate the difference between ‘rand’ and ‘randc’.

6. Demonstrate Random Control with randcase and $urandom_range.

7. Demonstrate 4-bit adder with the verification environment.

8. Design a UART using system Verilog

a. Design Transmitter logic.

b. Design Receiver logic.

c. Design a top level test bench

Textbook/ Textbooks

1 System Verilog for Verification – A guide to learning the Test bench language features Chris Spear Springer Publications Second Edition, 2010

Reference Books

1 System Verilog for Design- A guide to using system Verilog for Hardware design and modeling Stuart Sutherland, Simon Davidmann, Peter Flake Springer Publications Second Edition, 2006