MTech Advanced Digital Design syllabus for 1 Sem 2020 scheme 20SCE12

Module-1 Introduction 0 hours

Introduction:

Design methodology – An introduction; IC technology options

Module-2 Logic Design with Verilog 0 hours

Logic Design with Verilog:

Structural models of combinational logic; Logic simulation, Design verification, and Test methodology; Propagation delay; Truth-Table models of Combinational and sequential logic with Verilog.

A d v e r t i s e m e n t
Module-3 Logic Design with Behavioural Models 0 hours

Logic Design with Behavioural Models:

Behavioural modelling; A brief look at data types for Behavioural modelling; Boolean-Equation – Based Behavioural models of combinational logic; Propagation delay and continuous assignments; Latches and Level – Sensitive circuits in Verilog; Cyclic Behavioural models of Flip-Flops and Latches; Cyclic behaviour and edge detection; A comparison of styles for Behavioural modelling; Behavioural models of multiplexers, encoders, and decoders; Dataflow models of a Linear- Feedback Shift Register; Modelling digital machines with repetitive algorithms; Machines with multi-cycle operations; Design documentation with functions and tasks; Algorithmic state machine charts for Behavioural modelling; ASMD charts; Behavioural models of counters, shift registers and register files; Switch debounce, meta-stability and synchronizers for asynchronous signals; Design example

Module-4 Synthesis of Combinational and Sequential Logic 0 hours

Synthesis of Combinational and Sequential Logic:

Introduction to synthesis; Synthesis of combinational logic; Synthesis of sequential logic with latches; Synthesis of three-state devices and bus interfaces; Synthesis of sequential logic with flip-flops; Synthesis of explicit state machines; Registered logic; State encoding; Synthesis of implicit state machines, registers and counters; Resets; Synthesis of gated clocks and clock enables; Anticipating the results of synthesis; Synthesis of loops; Design traps to avoid; Divide and conquer: Partitioning a design.

Module-5 Programmable Logic and Storage Devices 0 hours

Programmable Logic and Storage Devices:

Programmable logic devices; storage devices; PLA; PAL; Programmability of PLDs; CPLDs; FPGAs; Verilog-Based design flows for FPGAs; Synthesis with FPGAs.

 

Course outcomes:

At the end of the course the student will be able to:

  • Work on various IC technology options.
  • Demonstrate logic simulation, Design verification, Verilog.
  • Work on Flip-Flops and Latches; multiplexers, encoders, and decoders, synchronizers for asynchronous signals.
  • Design and implement circuits on combinational logic; Registered logic; registers and counters; Resets; Divide and conquer: Partitioning a design.

 

Question paper pattern:

The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to 60.

  • The question paper will have ten full questions carrying equal marks.
  • Each full question is for 20 marks.
  • There will be two full questions (with a maximum of four sub questions) from each module.
  • Each full question will have sub question covering all the topics under a module.
  • The students will have to answer five full questions, selecting one full question from each module.

 

Textbook/ Textbooks

1 Advanced Digital Design with the Verilog HDL Michael D. Celetti PHI 2013

 

Reference Books

1 Digital Design –An Embedded Systems Approach Using VERILOG PeterJ. Asheden ELSEVIER 2013

2 Fundamentals of Digital Logic with Verilog Design Stephen Brown, ZvonkoVranesic Tata Mc-Graw Hill 2009

Categories

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