Principles of Combinational Logic:
Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps- up to 4 variables, Quine-McCluskey Minimization Technique.Quine- McCluskey using Don’t Care Terms. (Text 1, Chapter 3).
Logic Design with MSI Components and Programmable Logic Devices:
Binary Adders and Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices (PLDs), Programmable Read only Memories (PROMS). (Text 2, Chapter 5)
Flip-Flops:
Basic Bistable Elements, Latches, Timing Considerations, TheMaster-Slave Flip-flops (Pulse-Triggered flip-flops): SR flip-flops, JK flip-flops, Edge Triggered Flip-flops, Characteristic equations. (Text 2, Chapter 6)
SimpleFlip-Flops Applications:
Registers, Binary Ripple Counters, Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T , JK , D and SR flip-flops. (Text 2, Chapter 6)
Introduction to Verilog:
Structure of Verilog module, Operators, Data Types, Styles of Description- Data flow description, Behavioral description. Implementation of half adder and full adder using Verilog data flow description.
Verilog Behavioral description:
Structure, Variable Assignment Statement, Sequential Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1,4:1,8:1). (Text 3, Chapters:1, 2, 3)
Course Outcomes:
After studying this course, students will able to:
• Simplify Boolean functions using K-map and Quine-McCluskey minimization technique
• Analyze and design for combinational logic circuits.
• Analyze the concepts of Latches and Flip Flops. (SR, D, T and JK).
• Analyze and design the synchronous sequential circuits.
• Implement Combinational circuits (adders, subtractors, multiplexers) using Verilog descriptions.
Question Paper Pattern
• The question paper will have TEN questions.
• Each full question carry 20 marks
• There will be TWO full questions (with maximum of THREE sub questions) from each module.
• Each full question will have sub questions covering all the topics under a module.
• The students will have to answer FIVE full questions, selecting ONE full question from each module.
Textbooks:
1. Digital Logic Applications and Design by John M Yarbrough, Thomson Learning,2001
2. Digital Principles and Design by Donald D. Givone, McGraw Hill, 2002.
3. HDL Programming VHDL and Verilog by Nazeih M. Botros, 2009 reprint, Dreamtech press.
Reference Books:
1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning
2. Digital Principles and Design – Donald D Givone,12threprint, TMH,2008
3. Logic Design, Sudhakar Samuel, Pearson/ Saguine, 2007
4. Fundamentals of HDL- Cyril P R Pearson/Sanguin 2010