Moore’s law, speed power performance, nMOS fabrication, CMOS fabrication: n-well, p-well processes, BiCMOS, Comparison of bipolar and CMOS.
Basic Electrical Properties of MOS And BiCMOS Circuits:
Drain to source current versus voltage characteristics, threshold voltage, transconductance.
Basic Electrical Properties of MOS And BiCMOS Circuits:
nMOS inverter, Determination of pull up to pull down ratio, nMOS inverter driven through one or more pass transistors, alternative forms of pull up, CMOS inverter, BiCMOS inverters, latch up.
Basic Circuit Concepts:
Sheet resistance, area capacitance calculation, Delay unit, inverter delay, estimation of CMOS inverter delay, driving of large capacitance loads, super buffers, BiCMOS drivers.
MOS and BiCMOS Circuit Design Processes:
MOS layers, stick diagrams, nMOS design style, CMOS design style, design rules and layout, λ - based design.
Scaling of MOS Circuits:
scaling factors for device parameters, limitations of scaling.
Subsystem Design and Layout-1 :
Switch logic pass transistor, Gate logic inverter, NAND gates, NOR gates, pseudo nMOS, Dynamic CMOS, example of structured design, Parity generator, Bus arbitration, multiplexers, logic function block, code converter.
Subsystem Design and Layout-2 :
Clocked sequential circuits, dynamic shift registers, bus lines, subsystem design processes, General considerations, 4-bit arithmetic processes, 4-bit shifter.
Design Process-Computational Elements:
Regularity, design of ALU subsystem, ALU using adders, carry look ahead adders, Multipliers, serial parallel multipliers, Braun array, Bough – Wooley multiplier.
Memory, Register and Aspects of Timing:
Three Transistor Dynamic RAM cell, Dynamic memory cell, Pseudo- Static RAM, JK Flip-flop, D Flip-flop circuits, RAM arrays, practical aspects and testability: Some thoughts of performance, optimization and CAD tools for design and simulation.
Course Outcomes:
After studying this course, students will able to;
1. Identify the CMOS layout levels, and the design layers used in the process sequence.
2. Describe the general steps required for processing of CMOS integrated circuits.
3. Design static CMOS combinational and sequential logic at the transistor level.
4. Demonstrate different logic styles such as complementary CMOS logic, pass-transistorLogic, dynamic logic, etc.
5. Interpret the need for testability and testing methods in VLSI.
Question Paper Pattern:
• The question paper will have TEN questions.
• Each full question carry 20 marks
• There will be TWO full questions (with maximum of THREE sub questions) from each module.
• Each full question will have sub questions covering all the topics under a module.
• The students will have to answer FIVE full questions, selecting ONE full question from each module.
Textbook:
1. Basic VLSI Design -3rd Edition, Douglas APucknell, Kamaran Eshraghian, Prentice Hall of India publication, 2005.
Reference Books:
1. CMOS Digital Integrated Circuits, Analysis And Design, 3rd Edition, Sung – Mo (Steve) Kang, Yusuf Leblbici, Tata McGraw Hill, 2002.
2. VLSI Technology - S.M. Sze, 2nd edition Tata McGraw Hill, 2003.