The RISC design philosophy; The ARN design philosophy; Embedded system hardware and software.ARM processor fundamentals: Registers; Current Program Status Register; Pipeline; Exceptions, interrupts and the Vector Table; Core extensions; Architecture revisions; ARM processor families.
ARM instruction set: Data processing instructions; Branch instructions; Load-store instructions; Software interrupt instruction; Program Status Register functions; Loading constants; ARMv5E extensions; Conditional execution.Thumb instruction set: Thumb register usage; ARM –Thumb interworking; Other branch instructions; Data processing instructions; Single-Register Load-Store instructions; Multiple-Register Load-Store instructions; Stack instructions; Software interrupt instruction.
Writing assembly code; Profiling and cycle counting; Instruction scheduling; Register allocation; Conditional execution; Looping constructs; Bit manipulation; Efficient switches; Handling unaligned data.
Double-precision integer multiplication; Integer normalization and count leading zeros; Division; Square roots; Transcendental functions; Endian reversal and bit operations; Saturated and rounded arithmetic; Random number generation.
Exception handling; Interrupts and interrupt handling schemes
The memory hierarchy and the cache memory; Cache architecture; Cache policy; Coprocessor 15 and cache; Flusing and cleaning cache memory; Cache lockdown; Caches and software performance.
Memory Protection Units: Protected regions; Initializing the MPU, cache and write buffer; Demonstration of an MPU system. Memory Management Units: Moving from MPU to an MMU; How virtual memory works; Details of the ARM MMU.
Page tables; The translation lookaside buffer; Domains and memory access permission; The caches and write buffer; Coprocessor 15 and MMU configuration; The fast context switch extension.