06ESL38 LOGIC DESIGN LAB syllabus for EC


Unit-1 0 hours

Simplification, realization of Boolean expressions using logic gates/Universal gates.

Unit-2 0 hours

Realization of Half/Full adder and Half/Full Subtractors using logic gates.

Unit-3 0 hours

(i) Realization of parallel adder/Subtractors using 7483 chip (ii) BCD to Excess-3 code conversion and vice versa.

Unit-4 0 hours

Realization of Binary to Gray code conversion and vice versa

Unit-5 0 hours

MUX/DEMUX – use of 74153, 74139 for arithmetic circuits and code converter.

Unit-6 0 hours

Realization of One/Two bit comparator and study of 7485 magnitude comparator.

Unit-7 0 hours

Use of a) Decoder chip to drive LED display and b) Priority encoder.

Unit-8 0 hours

Truth table verification of Flip-Flops: (i) JK Master slave (ii) T type and (iii) D type.

Unit-9 0 hours

Realization of 3 bit counters as a sequential circuit and MOD – N counter design (7476, 7490, 74192, 74193).

Unit-10 0 hours

Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95.

Unit-11 0 hours

Wiring and testing Ring counter/Johnson counter.

Unit-12 0 hours

Wiring and testing of Sequence generator.

Last Updated: Tuesday, January 24, 2023