06ECL48 HDL LAB syllabus for EC


Unit-1 PROGRAMMING (using VHDL and Verilog) 0 hours

Write HDL code to realize all the logic gates

Unit-2 PROGRAMMING (using VHDL and Verilog) 0 hours

Write a HDL program for the following combinational designs a.2 to 4 decoder b.8 to 3 (encoder without priority & with priority) c.8 to 1 multiplexer d.4 bit binary to gray converter e.Multiplexer, de-multiplexer, comparator.

Unit-3 PROGRAMMING (using VHDL and Verilog) 0 hours

Write a HDL code to describe the functions of a Full Adder Using three modeling styles.

Last Updated: Tuesday, January 24, 2023

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