Why HDL? , A Brief History of HDL, Structure of HDL Module, Operators, Data types, Types of Descriptions, simulation and synthesis, Brief comparison of VHDL and Verilog
Highlights of Data-Flow Descriptions, Structure of Data-Flow Description, Data Type – Vectors.
Behavioral Description highlights, structure of HDL behavioral Description, The VHDL variable –Assignment Statement,sequential statements.
Highlights of structural Description, Organization of the structural Descriptions, Binding, state Machines, Generate, Generic, and Parameter statements.
Highlights of Procedures,tasks, and Functions, Procedures and tasks, Functions. Advanced HDL Descriptions: File Processing, Examples of File Processing
Why Mixed-Type Description? VHDL User-Defined Types, VHDL Packages, Mixed-Type Description examples
Highlights of Mixed-Language Description, How to invoke One language from the Other, Mixed-language Description Examples, Limitations of Mixed-Language Description.
Highlights of Synthesis, Synthesis information from Entity and Module, Mapping Process and Always in the Hardware Domain.