10EC56 Fundamentals of CMOS VLSI syllabus for EC


Part A
Unit-1 BASIC MOS TECHNOLOGY 7 hours

BASIC MOS TECHNOLOGY: Integrated circuit’s era. Enhancement and depletion mode MOS transistors. nMOS fabrication. CMOS fabrication. Thermal aspects of processing. BiCMOS technology. Production of E-beam masks. 3 Hrs MOS TRANSISTOR THEORY: Introduction, MOS Device Design Equations, The Complementary CMOS Inverter – DC Characteristics, Static Load MOS Inverters, The Differential Inverter, The Transmission Gate, Tristate Inverter. 4 Hrs

Unit-2 CIRCUIT DESIGN PROCESSES 7 hours

CIRCUIT DESIGN PROCESSES: MOS layers. Stick diagrams. Design rules and layout – lambda-based design and other rules. Examples. Layout diagrams. Symbolic diagrams. Tutorial exercises.4 Hrs Basic Physical Design of Simple logic gates.3 Hrs

Unit-3 CMOS LOGIC STRUCTURES 6 hours

CMOS Complementary Logic, Bi CMOS Logic, Pseudo-nMOS Logic, Dynamic CMOS Logic, Clocked CMOS Logic, Pass Transistor Logic, CMOS Domino Logic Cascaded Voltage Switch Logic (CVSL).

Unit-4 BASIC CIRCUIT CONCEPTS 6 hours

BASIC CIRCUIT CONCEPTS: Sheet resistance. Area capacitances. Capacitance calculations. The delay unit. Inverter delays. Driving capacitive loads. Propagation delays. Wiring capacitances.3 Hrs SCALING OF MOS CIRCUITS: Scaling models and factors. Limits on scaling. Limits due to current density and noise.3 Hrs

Part B
Unit-5 CMOS SUBSYSTEM DESIGN 7 hours

CMOS SUBSYSTEM DESIGN: Architectural issues. Switch logic. Gate logic. Design examples – combinational logic. Clocked circuits. Other system considerations.5 Hrs Clocking Strategies2 Hrs

Unit-6 CMOS SUBSYSTEM DESIGN PROCESSES 6 hours

General considerations. Process illustration. ALU subsystem. Adders. Multipliers.

Unit-7 MEMORY, REGISTERS AND CLOCK 6 hours

Timing considerations. Memory elements. Memory cell arrays.

Unit-8 TESTABILITY 7 hours

Performance parameters. Layout issues. I/O pads. Real estate. System delays. Ground rules for design. Test and testability.

Last Updated: Tuesday, January 24, 2023