18EC72 VLSI Design syllabus for EC



A d v e r t i s e m e n t

Module-1 Introduction 8 hours

Introduction:

A Brief History, MOS Transistors, CMOS Logic (1.1 to 1.4 of TEXT2)

MOS Transistor Theory:

Introduction, Long-channel I-V Characteristics, Non-ideal I-V Effects, DC Transfer Characteristics (2.1, 2.2, 2.4 and 2.5 of TEXT2).

Module-2 Fabrication 8 hours

Fabrication:

CMOS Fabrication and Layout, VLSI Design Flow, Introduction, CMOS Technologies, Layout Design Rules, (1.5 and 3.1 to 3.3 of TEXT2).

MOSFET Scaling and Small-Geometry Effects, MOSFET Capacitances (3.5 to 3.6 ofTEXT1),

Module-3 Delay 8 hours

Delay:

Introduction, Transient Response, RC Delay Model, Linear Delay Model, Logical Efforts of Paths (4.1 to 4.5 ofTEXT2, except sub-sections 4.3.7, 4.4.5, 4.4.6, 4.5.5 and 4.5.6).

Combinational Circuit Design:

Introduction, Circuit families (9.1to 9.2 of TEXT2, except subsection 9.2.4).,

Module-4 Sequential Circuit Design 8 hours

Sequential Circuit Design:

Introduction, Circuit Design for Latches and Flip­ Flops (10.1 and 10.3.1to 10.3.4 of TEXT2)

Dynamic Logic Circuits:

Introduction, Basic Principles of Pass Transistor Circuits, Synchronous Dynamic Circuit Techniques, Dynamic CMOS Circuit Techniques (9.1, 9.2, 9.4 to 9.5 of TEXT1),

Module-5 Semiconductor Memories 8 hours

Semiconductor Memories:

Introduction, Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), (10.1 to 10.3 of TEXT1)

Testing and Verification:

Introduction, Logic Verification Principles, Manufacturing Test Principles, Design for testability (15.1, 15.3, 15.515.6.1to 15.6.3of TEXT 2).

 

Course outcomes:

At the end of the course, the students will be able to:

1. Demonstrate understanding of MOS transistor theory, CMOS fabrication flow and technology scaling.

2. Draw the basic gates using the stick and layout diagrams with the knowledge of physical design aspects.

3. Demonstrate ability to design Combinational, sequential and dynamic logic circuits as per the requirements

4. Interpret Memory elements along with timing considerations

5. Interpret testing and testability issues in VLSI Design

 

Question paper pattern:

  • Examination will be conducted for 100 marks with question paper containing 10 full questions, each of 20 marks.
  • Each full question can have a maximum of 4 sub questions.
  • There will be 2 full questions from each module covering all the topics of the module.
  • Students will have to answer 5 full questions, selecting one full question from each module.
  • The total marks will be proportionally reduced to 60 marks as SEE marks is 60.

 

TEXTBOOKS:

1. ''CMOS Digital Integrated Circuits: Analysis and Design" - Sung Mo Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill.

2. "CMOS VLSI Design- A Circuits and Systems Perspective"- Neil H. E. Weste and David Money Harris, 4th Edition, Pearson Education.

 

REFERENCE BOOKS:

1. Adel Sedra and K. C. Smith, "Microelectronics Circuits Theory and Applications", 6th or 7th Edition, Oxford University Press, International Version, 2009.

2 DouglasAPucknell & Kamran Eshragian, ''Basic VLSIDesign", PHI 3rd Edition, (original Edition- 1994).

3. BehzadRazavi, ''Design of Analog CMOS Integrated Circuits", TMH, 2007.

Last Updated: Tuesday, January 24, 2023

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