21EC32 Digital System Design using Verilog syllabus for EC

Principles of Combinational Logic:

Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps- up to 4 variables, Quine-McCluskey Minimization Technique. Quine-McCluskey using Don’t Care Terms. (Section 3.1 to 3.5 of Text 1).

Logic Design with MSI Components and Programmable Logic Devices:

Binary Adders and Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices (PLDs) (Section 5.1 to 5.7 of Text 2)

Flip-Flops and its Applications:

The Master-Slave Flip-flops (Pulse-Triggered flip-flops): SR flip-flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T, JK, D and SR flip-flops. (Section 6.4, 6.6 to 6.9 (Excluding 6.9.3) of Text 2)

Introduction to Verilog:

Structure of Verilog module, Operators, Data Types, Styles of Description. (Section 1.1 to 1.6.2, 1.6.4 (only Verilog), 2 of Text 3) Verilog Data flow description: Highlights of Data flow description, Structure of Data flow description. (Section 2.1 to 2.2 (only Verilog) of Text 3)

Verilog Behavioral description:

Structure, Variable Assignment Statement, Sequential Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1). (Section 3.1 to 3.4 (only Verilog) of Text 3)

Verilog Structural description:

Highlights of Structural description, Organization of structural description, Structural description of ripple carry adder. (Section 4.1 to 4.2 of Text 3)

PRACTICAL COMPONENT OF IPCC

Using suitable simulation software, demonstrate the operation of the following circuits:

Experiments

1 To simplify the given Boolean expressions and realize using Verilog program.

2 To realize Adder/Subtractor (Full/half) circuits using Verilog data flow description.

3 To realize 4-bit ALU using Verilog program.

4 To realize the following Code converters using Verilog Behavioral description a) Gray to binary and vice versa b) Binary to excess3 and vice versa

5 To realize using Verilog Behavioral description: 8:1 mux, 8:3 encoder, Priority encoder

6 To realize using Verilog Behavioral description: 1:8 Demux, 3:8 decoder, 2-bit Comparator

7 To realize using Verilog Behavioral description: Flip-flops: a) JK type b) SR type c) T type and d) D type

8 To realize Counters - up/down (BCD and binary) using Verilog Behavioral description.

Demonstration Experiments (For CIE only – not to be included for SEE)

Use FPGA/CPLD kits for downloading Verilog codes and check the output for interfacing experiments.

9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor in the specified direction (by N steps).

10 Verilog programs to interface a Relay or ADC to the FPGA/CPLD and demonstrate its working.

11 Verilog programs to interface DAC to the FPGA/CPLD for Waveform generation.

12 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate its working.

Course Outcomes

At the end of the course the student will be able to:

1. Simplify Boolean functions using K-map and Quine-McCluskey minimization technique.

2. Analyze and design for combinational logic circuits.

3. Analyze the concepts of Flip Flops (SR, D, T and JK) and to design the synchronous sequential circuits using Flip Flops.

4. Model Combinational circuits (adders, subtractors, multiplexers) and sequential circuits using Verilog descriptions.

Assessment Details (both CIE and SEE)

• The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
• The minimum passing mark for the CIE is 40% of the maximum marks (20 marks).
• A student shall be deemed to have satisfied the academic requirements and earned the credits allotted to each subject/ course if the student secures not less than 35% (18 Marks out of 50) in the semester-end examination (SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together

CIE for the theory component of IPCC

Two Tests each of 20 Marks (duration 01 hour)

• First test at the end of 5th week of the semester
• Second test at the end of the 10th week of the semester

Two assignments each of 10 Marks

• First assignment at the end of 4th week of the semester
• Second assignment at the end of 9th week of the semester Scaled-down marks of two tests and two assignments added will be CIE marks for the theory component of IPCC for 30 marks.

CIE for the practical component of IPCC

• On completion of every experiment/program in the laboratory, the students shall be evaluated and marks shall be awarded on the same day. The 15 marks are for conducting the experiment and preparation of the laboratory record, the other 05 marks shall be for the test conducted at the end of the semester.
• The CIE marks awarded in the case of the Practical component shall be based on the continuous evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of all experiments’ write-ups are added and scaled down to 15 marks.
• The laboratory test (duration 03 hours) at the end of the 15th week of the semester /after completion of all the experiments (whichever is early) shall be conducted for 50 marks and scaled down to 05 marks.

Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory component of IPCC for 20 marks.

SEE for IPCC

Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for the course (duration 03 hours)

• The question paper will have ten questions. Each question is set for 20 marks.
• There will be 2 questions from each module. Each of the two questions under a module (with a maximum of 3 sub-questions), should have a mix of topics under that module.  The students have to answer 5 full questions, selecting one full question from each module. The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will have a CIE component only. Questions mentioned in the SEE paper shall include questions from the practical component.
• The minimum marks to be secured in CIE to appear for SEE shall be the 12 (40% of maximum marks-30) in the theory component and 08 (40% of maximum marks -20) in the practical component. The laboratory component of the IPCC shall be for CIE only. However, in SEE, the questions from the laboratory component shall be included. The maximum of 04/05 questions to be set from the practical component of IPCC, the total marks of all questions should not be more than the 20 marks. SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to qualify in the SEE. Marks secured out of 100 will be scaled down to 50 marks.

Suggested Learning Resources:

Text Books

1. Digital Logic Applications and Design by John M Yarbrough, Thomson Learning, 2001.

2. Digital Principles and Design by Donald D Givone, McGraw Hill, 2002.

3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dreamtech press.

Reference Books:

1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning

2. Logic Design, by Sudhakar Samuel, Pearson/ Sanguine, 2007

3. Fundamentals of HDL, by Cyril P R, Pearson/Sanguine 2010