Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps-3, 4 and 5 variables, Incompletely specified functions (Don’t Care terms), Simplifying Max term equations. [(Text book 1) 3.1, 3.2, 3.3, 3.4]
Quine-McCluskey minimization technique- Quine-McCluskey using don’t care terms, Reduced Prime Implicant Tables, Map entered variables [(Text book 1) 3.5, 3.6]
General approach, Decoders-BCD decoders, Encoders. [(Text book 1) 4.1, 4.3, 4.4]
Digital multiplexers- Using multiplexers as Boolean function generators. Adders and subtractors-Cascading full adders, Look ahead carry, Binary comparators. [(Text book 1) 4.5, 4.6 - 4.6.1, 4.6.2, 4.7]
Basic Bistable Element, Latches, SR Latch, Application of SR Latch, A Switch Debouncer, The Latch, The gated SR Latch, The gated D Latch, The Master-Slave Flip-Flops (Pulse-Triggered Flip-Flops): The Master-Slave SR Flip-Flops, The Master-Slave JK Flip-Flop, Edge Triggered Flip-Flop: The Positive Edge-Triggered D Flip-Flop, Negative-Edge Triggered D Flip-Flop. [(Text book 2) 6.1, 6.2, 6.4, 6.5]
Characteristic Equations, Registers, Counters - Binary Ripple Counters, Synchronous Binary counters, Counters based on Shift Registers, Design of a Synchronous counters, Design of a Synchronous Mod-6 Counter using clocked JK Flip-Flops Design of a Synchronous Mod-6 Counter using clocked D, T, or SR Flip-Flops [(Text book 2) 6.6, 6.7, 6.8, 6.9 – 6.9.1 and 6.9.2]
Introduction, Mealy and Moore Models, State Machine Notation, Synchronous Sequential Circuit Analysis, [(Text book 1) 6.1, 6.2, 6.3]
Construction of state Diagrams, Counter Design [(Text book 1) 6.4, 6.5]