Principles of combinational logic: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps- up to 4 variables, Quine-McCluskey minimization technique
Introduction to Verilog: Structure of Verilog module, Operators, data types, Styles of description- Data flow description, Behavioral description, Implement logic gates, half adder and full adder using Verilog data flow description.
Combinational Functions: Arithmetic Operations: Adders and subtractors-cascading full adders, Look ahead carry, Binary Comparators – 2 bit and 4 bit, two bit Multiplier, Verilog Description of for above circuits.
Multiplexers- Realization of 2:1, 4:1 and 8:1 using gates & Applications.
Demultiplexers: - Realization of 1:2 1:4 and 1:8 using basic gates & Applications
Verilog Behavioral description: Structure, variable assignment statement, sequential statements, loop statements, Verilog behavioral description of Multiplexers (2:1,4:1,8:1) and De-multiplexers (1:2,1:4,1:8)
Analysis and design of combinational logic: Encoders: Binary coded decimal codes, Binary – Gray vice versa, BCD – Excess 3 Encoders: Realization and Priority Encoders, Decoders: BCD – Decimal, BCD – Seven segment, Seven segment display.
Verilog behavioral description of Encoders (8 to 3 with priority and without priority), Decoders (2 to 4).
Sequential Logic Circuits-1:Latches and Flip-Flops: SR-latch, D-latch, D flip-flop, JK flip-flop, T flip- flop Master slave FF, Edge trigger and Pulse trigger FF , Registers and Shift Registers: PISO, PIPO, SISO,SIPO, Right shift and left shift, Universal Shift register.
Verilog behavioral description of latches (D-latch, SR latch) and flip-flops (D, T, JK, SR flip-flops).
Counters, design and their applications: Counters-Binary ripple counters, Synchronous binary counters, Modulo N counters – Synchronous and Asynchronous counters.
Verilog behavioral description of Synchronous and Asynchronous counters, sequential counters.
Synthesis of Verilog: Mapping process in the hardware domain- Mapping of signal assignment, variable assignment, if statements, else-if statements, loop statements