Laboratory Experiments:
Note: (1) Use discrete components to test and verify the logic gates. (2) Use FPGA/CPLD kits for down loading the Verilog code and test the output. Revised Bloom’s Taxonomy (RBT) Level
1. Simplification, realization of Boolean expressions using logic gates/Universal gates L1,L2,L3
2. To design and implement a) Adder/Subtractor – Full/half using logic gates. b) 4-bit Parallel Adder/ subtractor using IC 7483. L3, L4, L5,L6
3. To realize a) BCD to Excess-3 code conversion and vice versa b) Binary to Gray code conversion and vice versa L2,L3, L4
4. To realize a) 4:1 Multiplexer using gates b) 1:8 Demux c) Priority encoder and 3:8 Decoder using IC74138 d) One / Two bit comparator L2, L3, L4
5. To realize the following flip-flops using NAND Gates (a) T type (b) JK Master slave (c) D type L2, L3, L4
6. To realize the 3-bit counters as a sequential circuit and Mod-N Counter design (7476, 7490, 74192, 74193) L2, L3, L4
7. Adder/Subtractor – Full/half using Verilog data flow description L2, L3, L4
8. Code converters using Verilog Behavioral description a) Gray to binary and vice versa b) Binary to excess3 and vice versa L2, L3, L4
9. Multiplexers/decoders/encoder using Verilog Behavioral description - 8:1 mux, 3:8 decoder, 8:3 encoder, Priority encoder - 1:8 Demux and verify using test bench - 2-bit Comparator using behavioral description L2, L3, L4
10. Flip-flops using Verilog Behavioral description a) JK type b) SR type c) T type and d) D type L2, L3, L4
11. Counter up/down (BCD and binary) , sequential counters using Verilog Behavioral description L2,L3, L4
12. Interface experiments: (a) Stepper motor (b) Relay (c) Waveform generation using DAC L2,L3, L4