15MLL38 Digital Design and HDL Lab syllabus for ML

Simplification, realization of Boolean expressions using logic gates/Universalgates

To design and implement
a) Adder/Subtractor – Full/half using logic gates.
b) 4-bit Parallel Adder/ subtractor using IC 7483.

To realize
a) BCD to Excess-3 code conversion and vice versa
b) Binary to Gray code conversion and vice versa

To realize
a) 4:1 Multiplexer using gates
b) 1:8 Demux
c) Priority encoder and 3:8 Decoder using IC74138
d) One / Two bit comparator

To realize the following flip-flops using NAND Gates
(a) T type
(b) JK Master slave
(c) D type

To realize the 3-bit counters as a sequential circuit and Mod-N Counter design(7476, 7490, 74192, 74193)

Adder/Subtractor – Full/half using Verilog data flow description

Code converters using Verilog Behavioral description
a) Gray to binary and vice versa
b) Binary to excess3 and vice versa

Multiplexers/decoders/encoder using Verilog Behavioral description
- 8:1 mux, 3:8 decoder, 8:3 encoder, Priority encoder
- 1:8 Demux and verify using test bench
- 2-bit Comparator using behavioral description

Flip-flops using Verilog Behavioral description
a) JK type
b) SR type
c) T type
and d) D type

Counter up/down (BCD and binary) , sequential counters using VerilogBehavioral description

Interface experiments:
(a) Stepper motor
(b) Relay
(c) Waveform generationusing DAC